Index terms for OER course on IT Systems
B
Bus variants (Computer Architecture)
C
Control unit (Computer Architecture)
CPU core (Computer Architecture)
F
Fetch-decode-execute cycle (Computer Architecture)
H
Hack ALU
Registers (Computer Architecture)
Hack computer
Chip (Computer Architecture)
Hack CPU
Chip (Computer Architecture)
Implementation (Computer Architecture)
Registers (Computer Architecture)
Hack memory
Chip (Computer Architecture)
Instruction memory (Computer Architecture)
ROM (Computer Architecture)
Harvard architecture (Computer Architecture)
Hyper-threading (Computer Architecture)
I
I/O processing
Interrupts (Computer Architecture)
Polling (Computer Architecture)
Input/output (I/O) devices (Computer Architecture)
M
Memory mapped I/O
Hack memory chip (Computer Architecture)
Memory wall (Computer Architecture)
Memory
Von Neumann architecture (Computer Architecture)
Moore's law
Future (Computer Architecture)
Numbers (Computer Architecture)
Quote (Computer Architecture)
P
Parallel programming (Computer Architecture)
Pipelining (Computer Architecture)
R
Register
Hack CPU (Computer Architecture)
S
Speculative execution (Computer Architecture)
Stored program concept (Computer Architecture)
V
Von Neumann architecture
Bottleneck (Computer Architecture)
Sketch of architecture (Computer Architecture)
Stored program concept (Computer Architecture)
Author: Jens Lechtenbörger
Created: 2024-09-26 Thu 14:34
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