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Computer Structures and Operating Systems 2022
Dr. Jens Lechtenbörger (License Information)
von Neumann Architecture
Figure by Kapooht under CC BY-SA 3.0; converted from Wikimedia Commons
(e.g., PC, smartphone)
• RAM for data, ROM for instructions
• Physical RAM addresses
• No secondary memory
• RAM for data and instructions
• Physical and virtual addresses
• Memory hierarchy (disks)
• Single core
• Single mode of execution
• Neither cache nor MMU
• Multiple protection domains
• Caches and MMU
• No interrupts
• Polling for I/O (recall keyboard)
• Interrupts, DMA
• Different options for I/O
• Language library
• Single thread, no multitasking
• No virtual memory
• Real OSs with system calls
• Multitasking, scheduling
• Virtual memory
I/O happens synchronously while OS polls for result
int 0x80leads into kernel mode
0x80points to handler function
system_call, since 2015
This task is available for self-study in Learnweb.
Measurements for DRAM-based storage prototype (data from [YMH12])
This document is part of an Open Educational Resource (OER) course on Operating Systems. Source code and source files are available on GitLab under free licenses.
Except where otherwise noted, the work “OS02: Interrupts and I/O”, © 2017-2022 Jens Lechtenbörger, is published under the Creative Commons license CC BY-SA 4.0.
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In particular, trademark rights are not licensed under this license. Thus, rights concerning third party logos (e.g., on the title slide) and other (trade-) marks (e.g., “Creative Commons” itself) remain with their respective holders.